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DAMC-UNIZUP

Board Description

DAMC-UNIZUP is a high-end digital interface board in MTCA.4 form factor based on the Zynq UltraScale+ MPSoC. The board is intended to host data processing logic for a multi-channel Beam Position Monitor implemented on a RTM. Emphasis has been put on a flexible, high-performance Zone 3 interface. It is realized according to the DESY RTM class D1.2 or D1.3 standard (assembly option) and provides 4 (8) high-performance serial transceiver links and 38 (28) LVDS lanes. The board is optimized for the FPGAs Xilinx ZU7EG. The programmable resources features 504k logic cells, 1728 DSP slices and 20 Multi-Gigabit Transceivers. The Programmable System is based on a dual- or quad-core ARM Cortex-A53 operating at 1.2 GHz. Migration options to larger FPGAs with faster CPU and interface speeds are foreseen. This includes ZU11EG variants.

The Board can be configured do D1.2 Standard (default) or D1.3 Standard (assembly variant on request). D1.2 has 4 MGTs and 38 LVDS pairs D1.3 has 8 MGTs and 28 LVDS pairs

Features

  • FPGA: Xilinx UltraScale+ MPSoC XCZU7EG-1FFVC1156E with assembly option for XCZU11EG-1FFVC1156E
  • XCZU7EG has 504k Logic Cells, 1728 DSP Slices
  • EG type: 1.2 GHz Quad-Core ARM Cortex-A53 (with MALI-400 GPU)
  • 20 GTH transceivers (12.5 Gbps) and 4 GTR transceivers (6.0 Gbps) routed to SATA links and USB/DisplayPort
  • 11.0 MiB of BlockRAM, 27.0 MiB of UltraRAM
  • Four SFP+ slots on the front panel
  • 8 Gigabytes of on-board memory:
  • 64-bit 4 GiB DDR4 with 2400 MT/s on PS (accessible from PL via AXI interface (*1))
  • 64-bit 4 GiB DDR4 with 2400 MT/s on PL (accessible from PS via AXI interface)
  • Front-panel interlock/trigger Input and full MLVDS and interlock receive/drive capability
  • Flexible clocking with capability to receive MTCA backplane clocks (TCLKA, TCLKB) and 3 DSPLLs/PLLs to generate clocks for FPGA and transceivers and Front Panel Clock input (SMA)
  • 8 LVDS trigger inputs/outputs on the front panel
  • SD 3.0 Card slot with High-Speed Interface (> 100 MB/s) accessible via front panel and 8GB eMMC memory connected to PS
  • USB C-Type connector at the front panel that provides DisplayPort signals and USB 3.0 interface.
  • Zone 3 Class D1.2 (or D1.3) compliance with full interlock support
  • JTAG support from on-board connector or AMC backplane (JSM) with FPGA and RTM as targets
  • Full HPM update functionality

Licensing

This board is licensed to Instrumentation Technologies. For more details, please visit the page here.